According to these results the power GaN seems more
According to these results, the power GaN seems more robust than existing technologies (VDMOS, Superjunction, IGBT,) [5,10] and . Comparing with the SiC technology, the previous works show a low SEE tolerance [, , ] and . The SOA of power GaN devices can be equivalent to the IGBT trench  for the Burnout phenomenon but this technology is more vulnerable to SEGR because of the presence of SiO2 under the gate, in addition this trench technology is limited by its switching speed and cannot be used in all current applications especially space systems that requires high switching frequencies. Hence the importance of conducting more investigation on the GaN technology.
Introduction PLC (Programmable Logic Controller) has been widely used to develop digital I&Cs in nuclear power plants. The sharply-rising maintenance cost, however, as well as several problems such as the lower computation power, cyber-security (Regulatory Guide 5.71, 2010, IEC62645, 2014) and common cause failure (CCF), have requested for alternative solutions, i.e., FPGA (Field-Programmable Gate Array) (TR-1019181, 2009, TR-1022983, 2011, Survey of the CPLD/FPGA Technology, 2009). FPGA is able to provide the higher computation power than PLC with lower hardware cost and also provides the TWS119 of systems (Yoo and Seong, 2002, Kelly and Murphy, 1990). Many researches now try to use FPGA as an implementation platform of digital I&Cs (Yoo et al., 2013, Choi and Lee, 2012, Bakhmach et al., 2010, Hayashi et al., 2014, Clarkson, 2008, She and Jiang, 2009, sook Jang et al., 2008). FPGA has a different development process from PLC (Yoo et al., 2013), since it is a hardware-based platform. An FPGA design (i.e., software) is first designed with HDL (Hardware Description Language) such as Verilog (2001) and VHDL (2008), and then is subsequently synthesized into gate-level designs and physical layouts by FPGA logic synthesis and P&R tools, mechanically (Brown and Rose, 1996). Commercial FPGA logic synthesis tools (e.g., ‘Synplify Pro’ (Synopsys, 2015), ‘Precision RTL’ (Mentor Graphics, 2015a) and ‘Encounter RTL Compiler’ (Cadence, Encounter Conformal LEC, 2015) and FPGA EDAs (e.g., ‘Xilinx ISE Design Suit’ (Xilinx ISE design suite, 2015), ‘Altera Quartus 2’ (Altera Quartus 2, 2015) and ‘Actel Microsemi Libero SoC’ (Microsemi Libero SoC, 2015) make the synthesis almost mechanical. All software (also hardware) used directly as a safety-grade controller or indirectly to develop them should be developed and maintained under quality assurance programs such as 10CFR50 App.B (U.S. Code of Federal Regulations) or NQA-1 certification (The American Society of Mechanical Engineers, 2015), or should be certificated/selected by appropriate standards (Andryushin et al., 2014). If not, they should be dedicated through international reports/guidelines such as EPRI NP-5652 (2014) and TR-106439 (1996). The Korean regulatory also requires to comply with KINS/RG-17.12 (2011), which is based on them above. The FPGA logic synthesis tools mentioned above are widely recognized by many researchers and organizations (e.g., SCC (Software Certification Consortium) (SCC) as an item which should be dedicated strictly, since they produce FPGA hardware designs mechanically without human intervention. The problem we now face is that the reports/guidelines EPRI NP-5652/TR-106439 do not specifically incorporate the indirect COTS SW such as FPGA logic synthesis tools. They provide a well-defined process for dedication, but focus on commercial-grade (hardware) items, which directly compose safety-grade controllers. Even if an supplementary report EPRI TR-1025243 (2013) has recently been proposed to resolve the case of indirect software specifically, open community still judges that these tools are not the subject of COTS SW dedication, contrary to expectations. The general consensus (SCC, Santhanam, 2002, Evaluation of Guidance for Tools, 2015) among the industry is that FPGA logic synthesis tools should be dedicated more strictly than other indirect COTS SW.