Archives

  • 2018-07
  • 2018-10
  • 2018-11
  • 2019-04
  • 2019-05
  • 2019-06
  • 2019-07
  • 2019-08
  • 2019-09
  • 2019-10
  • 2019-11
  • 2019-12
  • 2020-01
  • 2020-02
  • 2020-03
  • 2020-04
  • 2020-05
  • 2020-06
  • 2020-07
  • 2020-08
  • The paper is organized as follows http www apexbt

    2020-07-23

    The paper is organized as follows. Section 2 gives a brief presentation of the JPEG-LS algorithm and respective hardware implementation. In Section 3 the fault injection model and the simulation-based susceptibility analysis method are reviewed. Section 4 provides a discussion on the susceptibility evaluation results for a reference description and for a tolerant description of the JPEG-LS agomelatine algorithm. The synthesis results are presented in Section 5, scrubbing process is included and evaluated in Section 6 and the conclusions are exposed in Section 7.
    JPEG-LS standard JPEG-LS international standard defines a set of lossless or near-lossless compression methods for the coding of still images [20]. The Low Complexity Lossless Compression for Images (LOCO-I) algorithm [21] is the basis of the JPEG-LS standard. A block diagram of LOCO-I algorithm is represented in Fig. 1. An important control parameter of this algorithm, named NEAR, defines the amount of near-lossless compression (NEAR=0 for lossless compression). The modeling approach is based on the notion of “contexts”, where, for each sample x, a context is determined by the gradients of the neighboring reconstructed samples a, b, c, and d. At the flat regions of the image, if the context estimates that neighboring samples are nearly identical, then the processing is switched to Run mode, otherwise the Regular mode is maintained. In Regular mode, a predictor combines the reconstructed samples, a, b, c, and d, to form a prediction of x. Under a context-based process, the prediction error is computed and then encoded with a modified Golomb code. In Run mode, the encoder seeks for a sequence of consecutive samples nearly identical to the reconstructed sample a starting at x. The run ends when this condition is no more verified or by the end of the current line, whichever comes first. Run count is then encoded.
    Random event injection and error rate evaluation method In a general sense, events produced in a space radiation environment have a mean incidence rate (as a function of ionized particle flux) and are uniformly distributed inside an electronic device [22]. The event generation and forced injection model of the simulation-based susceptibility analysis method is based on four assumptions:
    In this work, better susceptibility evaluation accuracy was achieved by improving the event injection to take into account the area and, in consequence, the incidence distribution probability due to word size of the different buffers implemented in the FPGA\'s RAM. Additionally, word sizes were also considered in the factor to correct the injection rate, in order to keep the same flux conditions for different target areas [19]. As exemplified in Fig. 4, the event generation and injection elements as well as the error-detecting and counting process are included in the VHDL code to be evaluated. INJ_COMB (transient) and INJ_REG (bit-flip) are signal injection elements, known as “saboteurs” [11], which may be in the form of components or behavioral declarations. The pulse rate is based on a mean period with a Gaussian distribution. The concept behind the Gaussian distribution is to have a spread event incidence and to define a mean event rate. Higher event rate campaigns can result in good statistical results in a shorter simulation time. An individual address is assigned to each injection point and, whenever a pulse is generated, addresses are selected randomly, one at a time. The address randomness is uniform so that events are evenly distributed. Injected transients result in a signal level inversion (“0” to “1” or “1” to “0”) for the duration of a pulse. After that, the signal returns to its previous level. Injected bit-flips result in an inversion that remains until the updating of the register or memory contents. It is wise to remind that modeling the electrical behavior of SETs in digital circuits is not an easy task [14]. As a simplification, a 1 ns pulse width, which can typically occur in harsh environments [23], is considered here. The logic masking is achieved by using adequate declarations inside an asynchronous process to generate a Gaussian random time interval between events. Thus, the incidence of pulses and the system clock are completely uncorrelated.